The invention relates to semiconductor devices, and, more particularly, to integrated circuit insulation and methods of fabrication.
Integrated circuits typically include field effect transistors with source/drains formed in a silicon substrate and insulated gates on the substrate plus multiple overlying metal (or polysilicon) interconnection levels with an insulating layer between the gates/sources/drains and the first metal level (premetal dielectric) and between successive metal levels (intermetal-level dielectric). Vertical vias in the insulating layers filled with metal (or polysilicon) provide connections between adjacent metal levels and between the gate/source/drain and the first metal level. Each insulating layer must cover the relatively bumpy topography of a metal level or the gates and field oxide, and the insulating layer must have a planar top surface for ease in formation of the next level metal. Consquently, various approaches to forming planar insulating layers over bumpy topography have been developed: reflowing deposited borophosphosilicate glass (BPSG), using spin-on glass (SOG), sputering while depositing in plasma enhanced chemical vapor deposition (PECVD) with tetraethoxysilane (TEOS), and etching back a stack of deposited glass plus spun-on planarizing photoresist.
These approaches have problems including the multiple steps required for fabrication of the insulating layer and gate dielectric breakdown from gate exposure to a plasma during PECVD TEOS used for premetal dielectric.
Laxman, Low ∈ Dielectrics: CVD Fluorinated Silicon Dioxides, 18 Semiconductor International 71 (May 1995), summarizes reports of fluorinated silicon dioxide for use as an intermetal level dielectric which has a dielectric constant lower than that of silicon dioxide (3.9). In particular, PECVD using silicon tetrafluoride (SiF4), silane (SiH4), and oxygen (O2) source gasses can deposit SiOXFY with up to 10% fluorine and a dielectric constant down towards 3.0.